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Logic level
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21	Preliminaries Frame Level Model Level A Modal Logic for Abstract Delta Modeling Frank de Boer Add to Reading List Source URL: www.mhelvens.net Language: English - Date: 2012-09-02 13:47:35 Modal logic Non-classical logic Philosophical logic Conceptual model Metaphor Simulation Normal modal logic Delta
22	Hardware Synthesis using SAFL and Application to Processor Design (Invited Talk) Alan Mycroft1,2 and Richard Sharp1 1 Add to Reading List Source URL: rich.recoil.org Language: English - Date: 2006-04-13 14:58:00 Subroutines Hardware description languages Electronic design automation Electronic engineering High-level synthesis Hardware verification languages Verilog VHDL Logic synthesis Inline expansion Parameter Recursion
23	Computer Science Education 2004, Vol. 14, No. 3, pp. 235–248 Teaching Algorithm Efficiency at CS1 Level: A Different Approach Judith Gal-Ezer, Tamar Vilner, and Ela Zur Add to Reading List Source URL: www.openu.ac.il Language: English - Date: 2007-10-29 03:41:13 Theoretical computer science Analysis of algorithms Dynamic programming Software optimization Algorithm Mathematical logic Selection algorithm Recursion Sort Best worst and average case Knapsack problem Matrix chain multiplication
24	A concise guide to VMM Verification Methodology Version 1.2 VMM is available for free download at www.vmmcentral.org VMM Golden Reference Guide First Edition, January 2010 Copyright © 2010 by Doulos Ltd. All rights res Add to Reading List Source URL: vmmcentral.org Language: English - Date: 2010-03-04 18:39:33 Hardware verification languages Hardware description languages SystemVerilog Electronic design automation Logic design E Bus Functional Model Verilog Mentor Graphics Transaction-level modeling Reference Verification Methodology
25	Datasheet Synplify Pro and Premier Fast, Reliable FPGA Implementation and Debug Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2016-02-10 05:16:04 Electronic engineering Electronics Electronic design automation Electronic design System on a chip Fabless semiconductor companies Hardware description languages Logic synthesis Synopsys FPGA prototyping Field-programmable gate array High-level synthesis
26	ExCAPE Annual Report of Activities April 2014 to MarchOverview Add to Reading List Source URL: excape.cis.upenn.edu Language: English - Date: 2016-01-31 09:37:33 Theoretical computer science Electronic engineering Digital electronics Music Electronic design automation Formal verification Logic in computer science High-level synthesis Robotics Domain-specific language Finite-state machine Model checking
27	Soc Choice Welfare: 413–431 DOI: s00355z The mere addition paradox, parity and critical-level utilitarianism Mozaﬀar Qizilbash Add to Reading List Source URL: www.repugnant-conclusion.com Language: English - Date: 2007-06-24 16:35:53 Mathematics Logic Physics 1 Paradoxes Utilitarianism Mathematical logic Mere addition paradox Binary relation Equivalence relation Transitive relation Utility
28	MTP15N06VL Preferred Device Power MOSFET 15 Amps, 60 Volts, Logic Level N–Channel TO–220 Add to Reading List Source URL: instrumentation.obs.carnegiescience.edu Language: English - Date: 2009-11-13 16:31:43
29	MAX200–MAX209/ MAX211/MAX213 +5V, RS-232 Transceivers with 0.1μF External Capacitors Add to Reading List Source URL: datasheets.maximintegrated.com Language: English - Date: 2015-02-17 14:29:18 Electronic engineering Electronics Integrated circuits Electromagnetism Digital electronics Logic families RS-232 Telecommunications equipment IC power-supply pin Capacitor Logic level CMOS
30	Mostly-Automated Verification of Low-Level Programs in Computational Separation Logic Adam Chlipala Harvard University PLDI 2011 Add to Reading List Source URL: adam.chlipala.net Language: English - Date: 2016-01-02 15:47:17 Theoretical computer science Logic in computer science Formal methods Constraint programming Electronic design automation Satisfiability modulo theories Separation logic Mathematical logic Logic programming Logic

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